F)ĭRA75x, DRA74x Silicon Errata Automotive Infotainment Silicon Revision 2.0, 1.1 (Rev. View all 46ĭRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 datasheet (Rev. The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard. The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.Īdditionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code. Programmability is provided by dual-core Arm ® Cortex ®-A15 RISC CPUs with Arm ® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The devices also combine programmable video processing with a highly integrated peripheral set. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)ĭRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.Power, Reset, and Clock Management (PRCM).Up to 247 General-Purpose I/O (GPIO) pins.Dual Controller Area Network (DCAN) modules.PCI-Express ® 3.0 subsystems with two 5-Gbps lanes.Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD ®/SDIO).Three high-speed USB 2.0 dual-role devices.
#View contents of a vector code composer studio serial
Eight Multichannel Audio Serial Port (McASP) modules.Four Multichannel Serial Peripheral Interfaces (McSPI).Five Inter-Integrated Circuit (I 2C™) ports.Enhanced Direct Memory Access (EDMA) controller.General-Purpose Memory Controller (GPMC).Support for up to 10 multiplexed input ports.2D-graphics accelerator (BB2D) subsystem.HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant.Display controller with DMA engine and up to three pipelines.Up to two Embedded Vision Engines (EVEs).Dual Arm ® Cortex ®-M4 Image Processing Units (IPU).Two DDR2/DDR3/DDR3L memory interface (EMIF) modules.Level 3 (元) and level 4 (L4) interconnects.Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle.Fully object-code compatible with C67x and C64x+.Dual Arm ® Cortex ®-A15 microprocessor subsystem.Video, image, and graphics processing support.Architecture designed for infotainment applications.
0 kommentar(er)
